Reference is made to FIG. 1 which shows a schematic diagram of a standard memory circuit 10 including a plurality of memory cells 12 that are typically arranged in an array including plural columns and rows. Each memory cell 12 in this implementation is, for example, a conventional six transistor (6T) static random access memory (SRAM) cell 12. The memory circuit 10 further includes a wordline driver 14 for each row and an address decoder 16 configured to control operation of the wordline drivers.
Each memory cell 12 includes two cross-coupled CMOS inverters 22 and 24, each inverter including a series connected p-channel and n-channel MOSFET transistor pair. The inputs and outputs of the inverters 22 and 24 are coupled to form a latch circuit having a true data storage node QT and a complement data storage node QB. The cell 12 further includes two transfer (passgate) transistors 26 and 28 whose gate terminals are driven by a wordline (WL) that is coupled to an output of the wordline driver 14. Transistor 26 is source-drain connected between the true data storage node QT and a node associated with a true bitline (BLT). Transistor 28 is source-drain connected between the complement data storage node QB and a node associated with a complement bitline (BLB). The source terminals of the p-channel transistors 30 and 32 in each inverter 22 and 24 are coupled to receive a high supply voltage (for example, Vdd) at a high supply node, while the source terminals of the n-channel transistors 34 and 36 in each inverter 22 and 24 are coupled to receive a low supply voltage (for example, Gnd) at a low supply node. The high supply voltage Vdd at the high supply node and the low supply voltage Gnd at the low supply node comprise the power supply set of voltages for the cell 12.
The wordline driver circuit 14 includes a series connected p-channel and n-channel MOSFET transistor pair forming a logic inverter. The wordline driver circuit 14 is also coupled to receive the high supply voltage (Vdd) at the high supply node and is referenced to the low supply voltage (Gnd) at the low supply node. The input of the wordline driver circuit 14 is coupled to an output of the address decoder 16 and the wordline (WL) for a row of cells 12 is coupled to the output of the corresponding wordline driver circuit 14. The address decoder 16 receives an address (Addr), decodes the received address and selectively actuates the wordline through the wordline driver circuit 14.
The memory circuit 10 further includes a read assist circuit 40 coupled to each wordline (WL) or to pairs of wordlines. The functionality of the read assist circuit 40 is provided for use in read limited SRAM cells for operation at a supply voltage that is lower than a minimum functional voltage of the technology. One known technique for read assist is wordline lowering. In this technique, the wordline is pulled down by the read assist circuit 40 to a voltage lower than supply voltage in order to provide sufficient static noise margin (SNM) for the read and write operation. It will be noted that SNM varies with process, voltage and temperature (PVT), so it is important to track the word line underdrive (WLUD) voltage (a voltage lower than the wordline driver's high supply voltage Vdd) with PVT in order to achieve better power, performance and area (PPA) figures for the memory circuit.
The read assist circuit 40 as known in the art tracks wordline voltage lowering with process and temperature, but fails to track with respect to voltage. As SNM increases with increased supply voltage, this is an important factor not accounted for in prior art read assist circuits. Additionally, such tracking is important because the WLUD voltage increases as well with increased supply voltage, and thus can result in a slowdown of the read operation and also write failure. To protect against such a failure, there is an associated performance and power penalty and extra circuit architecture overhead.
There is accordingly a need in the art for an improved read assist circuit with process, voltage and temperature tracking capability.